This invention relates to electrical interconnection of integrated circuit chips and, particularly, to electrical interconnection of stacked die.
A typical semiconductor die has a front (“active”) side, in which the integrated circuitry is formed, a back side, and sidewalls. The sidewalls meet the front side at front edges and the back side at back edges. Semiconductor die typically are provided with interconnect pads (die pads) located at the front side for electrical interconnection of the circuitry on the die with other circuitry in the device in which the die is deployed. Typically, the die pads consist of an electrically conductive metal or metallization, such as copper or aluminum.
Some die as provided have die pads on the front side along one or more of the die margins, and these may be referred to as peripheral pad die. Other die as provided have die pads arranged in one or two rows on the front side near the center of the die, and these may be referred to as center pad die. Some die have pads arranged in an area array. However the die pads may be arranged in the die as provided, the die may be “rerouted” to provide a suitable arrangement of interconnect pads at or near one or more of the margins of the die.
A number of approaches have been proposed for increasing the density of active semiconductor circuitry in integrated circuit chip packages, while minimizing package size (package footprint, package thickness). In one approach to making a high density package having a smaller footprint, two or more semiconductor die, of the same or different functionality, are stacked one over another and mounted on a package substrate.
S. McElrea et al. U.S. application Ser. No. 12/124,077, filed May 20, 2008, titled “Electrically interconnected stacked die assemblies” describes stacked die configurations in which interconnect pads on the die are electrically connected by traces of an electrically conductive interconnect material. In some configurations adjacent die in the stack are provided with interconnect pads arranged at the front side along a die margin, and the edge at the margin of an overlying die is offset in relation to the margin of the die beneath it. The offset reveals at least a fraction of the area of the interconnect pads on the lower die, so that the pads on the lower die are available for electrical connection with pads on a die situated above. The electrically conductive interconnect material is an electrically conductive polymer, such as a curable conductive epoxy, for example. Larger stacked die assemblies may be made by constructing offset stacked die units in a modular design, and then stacking the units. One such modular unit may be inverted and mounted over another, with the interconnect ends of the respective modular units aligned and connected; the resulting two-tiered assembly presents a zig-zag configuration.
T. Caskey et al. U.S. application Ser. No. 12/124,097, filed May 20, 2008, titled “Electrical interconnect formed by pulse dispense” describes methods for electrical interconnection of die in a stack, and of stacked die with a substrate, by depositing an electrical interconnect material in situ in a series of pulses to form an electrically continuous interconnection. The interconnect material may be a curable material, and may be deposited in an uncured or partially cured state; and the material may be partially or additionally cured at an intermediate stage following dispense, and may be fully cured when dispense has been completed. Suitable interconnect materials include polymers filled with conductive material in particle form such as, for example, metal-filled polymers, including, for example metal filled epoxy, metal filled thermosetting polymers, metal filled thermoplastic polymers, or electrically conductive inks.